1. Field of the Invention
The present invention relates to an information processor that saves a plurality of addresses of errors occurring during bus cycles for prefetching memory operands.
2. Description of the Prior Art
Known information processors prefetch memory operands according to prefetched instructions to improve processing speed.
FIG. 1 is a view showing an essential part of a conventional information processor performing such a prefetching operation of memory operands.
In the information processor of FIG. 1, a memory operand is read out of an external storage device (not shown). A memory address corresponding to the memory operand to be read is stored in one register in an address register group (AP) according to a microinstruction. The memory address stored in the register group 1 is transferred to a memory address register (MAR) 5 according to an AP select signal given by a control logic 3, and the transferred memory address is latched in the memory address register (MAR) 5 according to an address latch signal given by the control logic 3. Then, the memory address is given to the external storage device.
According to the memory address, operand data is read out of the external storage device. After that, a bus cycle completion signal is externally given to the control logic 3. In synchronism with the bus cycle completion signal, the control logic 3 outputs a DP select signal to designate one register in a data storage register group 7 to store the read operand data in the designated register. In this way, the memory operand data is read out.
When the information processor accesses the external storage device in, for instance, the read operation, a bus cycle error may sometimes occur.
For example, when a parity error checking circuit in the external storage device detects an error or when a part of the external storage device where no access is allowed is accessed, a bus cycle error signal is generated to indicate the occurrence of bus cycle error. The bus cycle error is handled with an interrupt process. To activate the interrupt process, the information processor saves an address at which the bus cycle error occurred and delivers the address as interrupt information to an interrupt handler. Therefore, the address at which the bus cycle error occurred is given to a stack and stored therein.
In the arrangement of FIG. 1, if a bus cycle error occurs during the read of a memory operand, a bus cycle error signal is externally given to the control logic 3. Then, the control logic 3 provides an error address register (EAR) select signal synchronized with the bus cycle error signal to an error address register (EAR) group 9. Accordingly, the address of the bus cycle error stored in the memory address register (MAR) 5 and caused is given to and stored in one register in the error address register (EAR) group 9 that has been designated with the EAR select signal. Namely, the address stored in the memory address register (MAR) 5 is copied as an error address and stored in one register in the error address register group 9.
Meanwhile, the control logic 3 outputs an interrupt signal to activate an interrupt processing microprogram. According to this microprogram, the copied error address is read out of the error address register group 9 and pushed to a stack (not shown) via an internal bus 11.
The information processor that prefetches operand data as mentioned in the above does not always use the prefetched operand data. Therefore, the control logic 3 does not output an interrupt signal until the read operand data is actually used. In other words, at the time of prefetch, the control logic 3 does not output an interrupt signal even if a bus cycle error occurs in connection with the prefetch. Only when the data is needed, the interrupt signal is outputted to cope with the bus cycle error. Due to this, the number of error addresses supposed to be held in the error address register group 9 are equal to the number of prefetching operations.
The error address register group 9 of the information processor of FIG. 1 stores, therefore, addresses in equal number as those stored in the address register group 1. Namely, the error address register group 9 shall comprise registers of the same number as the number of registers contained in the address register group 1. Due to this, as the number of addresses to be stored in the address register group 1 increases, the scale of the error address register group 9 increases.